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february 2006 rev 9 1/24 24 stlc7550 low power low voltage analog front end features general purpose signal processing analog front end (afe) targeted for v.34bis modem and 56kbps modem applications 16-bit oversampling ? a/d and d/a converters 83db signal to noise ratio for sampling frequency up to 9.6khz @ 3v 87db dynamic range @ 3v filter bandwidths: 0.425 x the sampling frequency on-chip reference voltage single power supply range: 2.7 to 5.5v low power consumption less than 30mw operating power 3v stand-by mode power consumption less than 3mw at 3v programming sampling frequency max. sampling frequency : 45khz synchronous serial interface for processor datas exchange master or slave operations 0.50m cmos process tqfp48 package stlc7546 mode of operation compatible description the stlc7550 is a single chip analog front-end (afe) designed to implement modems up to 56kbps. it has been especially designed for host processing application in which the modulation software (v.34bis, 56kbps) is performed by the main application processor : pentium, risc or dsp processors. the main target of this device is stand alone appliances as hand held pc (hpc), personnal digital assistants (pda), webphones, network computers, set top boxes for digital television (satellite and cable). to comply with such ap plications stlc7550 is powered nominally at 3v only. maximum power dissipation 30mw is well suited for battery operations. in case of battery low, stlc7550 will cont inue to work even at a 2.7v level. stlc7550 also provides clock generator for all sampling frequencies requested for v.34bis and 56kbps applications. this new afe can also be used for pc mother boards or add-on cards or stand alone modems. it can be used in a master mode or slave mode. the slave mode eases multi afe architecture design in saving external logical glue. order codes (*) ecopack ? (see section 6 ) tqfp48 (7 x 7 x 1.4mm) (full plastic quad flat pack) part number temp range, cpackage packing stlc7550 tqf7 0 to 70 tqfp48 tube stlc7550 tqf7tr 0 to 70 tqfp48 tape & reel E-STLC7550TQF7 (*) 0 to 70 tqfp48 tube www.st.com obsolete product(s) - obsolete product(s)
content stlc7550 2/24 rev 9 content 1 pins description & block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.1 power supply (5 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.2 host interface (10 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.3 clock signals (2 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 analog interface (9 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 transmit d/a section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 transmit low pass filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 d/a converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 receive a/d section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 receive low pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 electrical specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 nominal dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 nominal ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.1 performance of the tx channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.2 smoothing filter transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5.1 performance of the rx channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 definition and terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 obsolete product(s) - obsolete product(s)
stlc7550 pins descript ion & block diagram rev 9 3/24 1 pins description & block diagram figure 1. pin connection (top view) table 1. pin list pin # pin name type description 1 - 2, 10 to 14, 22 to 26, 34 to 38, 46 to 48 nc - not connected 3 sclk o shift clock output 4 fs i/o frame synchronization input (slave)/output (master) 5 dv dd i positive digital power supply (2.7v to 5.5v) 6 dgnd i digital ground 7 mcm i master clock mode 8 xtalout o crystal output 9 xtalin/mclk i crystal input (mcm = 1) / external clock (mcm = 0) 15 hc1 i hardware control input 16 hc0 i hardware control input 17 pwrdwn i power down input 18 m/s i master/slave mode control pin input 19 v refp o 16-bit d/a and a/d positive reference voltage 20 v refn o 16-bit d/a and a/d negative reference voltage 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 33 12 34 35 36 13 14 15 16 17 18 19 20 21 22 23 24 44 43 42 41 40 39 38 37 45 46 47 48 agnd2 v cm av dd in- in+ auxin+ auxin- xtalin/mclk xtalout mcm dgnd dv dd fs sclk dout din tstd1 ts reset out- out+ agnd1 v refn m/s v refp pwrdwn hc0 hc1 obsolete product(s) - obsolete product(s)
pins description & block diagram stlc7550 4/24 rev 9 note: 1 to obtain published performance, the analog v dd and digital v dd should be decoupled with respect to analog ground and digital ground, respectively. the decoupling is intended to isolate digital noise from the analog section ; decoupling capacitors should be as close as possible to the respective analog and digital supply pins. 2 all the ground pins must be tied together. in the following section, the ground and supply pins are referred to as gnd and v dd , respectively. 1.1 pin description 1.1.1 power supply (5 pins) analog v dd supply (av dd ) this pin is the positive analog power supply voltage for the dac and the adc section. it is not internally connected to digital v dd supply (dv dd ). in any case the voltage on this pin must be higher or equal to the voltage of the digital power supply (dv dd ). digital vdd supply (dvdd) this pin is the positive digital power supply for dac and adc digital internal circuitry. analog ground (agnd1, agnd2) these pins are the ground return of the analog dac (adc) section. 21 agnd1 i analog ground 27 auxin+ i non-inverting input to auxiliary analog input 28 auxin- i inverting input to auxiliary analog input 29 in+ i non-inverting input to analog input amplifier 30 in- i inverting input to analog input amplifier 31 av dd i positive analog power supply (2.7v to 5.5v) 32 v cm o common mode voltage output (av dd /2) 33 agnd2 i analog ground 39 out+ o non-inverting smoothing filter output 40 out- o inverting smoothing filter output 41 reset i reset function to initialize the internal counters 42 ts i timeslot control input 43 tstd1 i/o digital input/output reserved for test 44 din i serial data input 45 dout o serial data output table 1. pin list (continued) pin # pin name type description obsolete product(s) - obsolete product(s)
stlc7550 pins descript ion & block diagram rev 9 5/24 digital ground (dgnd) this pin is the ground for dac and adc internal digital circuitry. 1.1.2 host interface (10 pins) data in (din) in data mode, the data word is the input of the dac channel. in software, the data word is followed by the control register word. data out (dout) in data mode, the data word is the adc conversion result. in software, the data word is followed by the register read. frame synchronization (fs) in master mode, the frame synchronization signal is used to indicate that the device is ready to send and receive data. the data transfer begins on the fa lling edge of the frame-sync signal. the framesync is generated internally and goes low on the rising edge of sclk in master mode. in slave mode the frame is generated externally. serial bit clock (sclk) sclk clocks the digital data into din and out of dout during the frame synchronization interval. the serial bit clock is generated internally. reset function (reset ) the reset function is to initialize the internal counters and control register. a minimum low pulse of 100ns is required to reset the chip. this reset function initiates the serial data communications. the reset function will initialize all the registers to their default value and will put the device in a pre-programmed st ate. after a low-going pulse on reset , the device registers will be initialized to provide an over-s ampling ratio equal to 16 0, the serial interface will be in data mode, the dac attenuation will be se t to infinite, the adc gain will be set to 0db, the differential input mode on the adc converter will be selected, and the multiplexor will be set on the main inputs in+ and in-. after a reset condition, the first frame synchronization corresponds to the primary channel. power down (pwrdwn ) the power-down input powers down the entire chip (< 50mw). when pwrdwn pin is taken low, the device powers down such that the existing internally programmed state is maintained. when pwrdwn is driven high, full operation resumes after 1ms. if the pwrdwn input is not used, it should be tied to v dd . hardware control (hc0, hc1) these two pins are used for hardware/software control of the device. the data on hc0 and hc1 will be latched on to the device on the rising edge of the frame synchronization pulse. if these two pins are low, software control mode is selected. when in software control mode, the lsb of the 16-bit word will select the data mode (lsb = 0) or the control mode (lsb = 1). other combinations of hc0/hc1 are for hardware control. these inputs should be tied low if not used. obsolete product(s) - obsolete product(s)
pins description & block diagram stlc7550 6/24 rev 9 master/slave control (m/s) when m/s is high, the device is in master mode and fs is generated internally. when m/s is low, the device is in slave mode and fs must be generated externally. master clock mode (mcm) when mcm is high, xtalin is provided externally and must be equal to 36.864mhz. when mcm is low, xtalin is provided externally and must be equal to oversampling frequency : fs x over (see figure 3 and section 2.4 ). timeslot control (ts) when ts = 0 the data are assigned to the firs t 16 bits after falling edge of fs (7546 mode) otherwise the data are bits 17 to 32. the case m/s = 1 with ts = 1 is reserved for life-test (transmit gain fixed to 0db). 1.1.3 clock signals (2 pins) depending on mcm value, these pins have different function. mcm = 1 (xtalin, xtalout) these pins must be tied to external crystal. for the value of crystal see section 2.3 . mcm = 0 (mclk, xtalout) mclk pin must be connected to an external clock. xtalout is not used. 1.1.4 analog interface (9 pins) dac and adc positive reference voltage output (v refp ) this pin provides the positive reference voltage used by the 16-bit converters. the reference voltage, v ref , is the voltage difference between the v refp and v refn outputs, and its nominal value is 1.25v. v refp should be externally decoupled with respect to v cm . dac and adc negative reference voltage output (v refn ) this pin provides the negative reference voltage used by the 16-bit converters, and should be externally decoupled with respect to v cm . common mode voltage output (v cm ) this output pin is the common mode voltage (av dd - agnd)/2. this output must be decoupled with respect to gnd. non-inverting smoothing filter output(out+) this pin is the non-inverting output of the fully differential analog smoothing filter. inverting smoothing filter output (out-) this pin is the inverting output of the fully differential analog smoothing filter. outputs out+ and outprovide analog signals with maximum peak-topeak amplitude 2 x vref, and must be followed by an external two pole smoothing f ilter. the external filter follows the internal single pole switch capacitor filter. the cutoff frequency of the external filter must be greater obsolete product(s) - obsolete product(s)
stlc7550 pins descript ion & block diagram rev 9 7/24 than two times the sampling frequency (fs), so that the combined frequency response of both the internal and external filters is flat in the passband. the attenuator of the last output stage can be programmed to 0db, 6db or infinite. non-inverting analog input (in+) this pin is the differential non-inverting adc input. inverting analog input (in-) this pin is the differential inverting adc input. these analog inputs (in+, in-) are presented to the sigma-delta modulator. the analog input peak-topeak differential signal range must be less than 2 x v ref , and must be preceded by an external single pole anti-aliasing filter. the cut-off frequency of the filter must be lower than one half the oversampling frequency. these filters should be set as close as possible to the in+ and in- pins. the gain of the first stage is programmable (see ta b l e 4 ). non-inverting auxiliary analog input (aux in+) this pin is the differential non-inverting auxili ary adc input. the characteristics are same as the in+ input. inverting auxiliary analog input (aux in-) this pin is the differential inverting auxiliary adc input. the characteristics are same as the in- input. the input pair (in+/in- or aux in+/aux in-) are software selectable. figure 2. block diagram analog modulator 2nd order modulator low-pass (0.425 x sampling frequency) hc0 out+ out- v cm v refn v refp in+ in- (0 + 6db in diff. input) dac 1 bit first order differential switched capacitor filter low-pass (0.425 x sampling frequency) serial ports and control register atten. 0db/+6db/ infinite m/s fs sclk dout din clock generator xtalin xtalout agnd2 agnd1 av dd dv dd dgnd stlc7550 reset pwrdwn 41 17 6 5 9 8 33 21 31 40 39 32 20 19 30 29 16 ts 7 mcm 42 hc1 15 18 4 3 45 44 tstd1 43 auxin+ auxin- 28 27 mux obsolete product(s) - obsolete product(s)
functional description stlc7550 8/24 rev 9 2 functional description 2.1 transmit d/a section the functions included in the tx d/a section are detailed hereafter. 16-bit 2?s complement data format is used in the dac channel. 2.1.1 transmit low pass filters the transmit low pass filter is basically an interp olating filter including a sinx/x correction. it is a combination of finite impulse response filter (fir) and an infinite impulse response filter (iir). the digital signal from the serial interface gets interpolated by 2, 3, 4, 5 or 6 x sampling frequency (fs) through the iir filter. the signal is further interpolated by 32 x fs x n (with n equal to 2, 3, 4, 5, 6) through the iir and fir filter. the low pass filter is followed by the dac. the dac is oversampled at 64, 96, 128, 160, 192 x fs. the oversampling ratio is user selectable. 2.1.2 d/a converter the oversampled d/a converter includes a second order digital noise shaper, a one bit d/a converter and a single pole analog low-pass filter. the attenuation of the last output stage can be programmed to 0db, +6db or infinite. the cut-off frequency of the single pole switch- capacitor lowpass is: with oclk = oversampling clock frequency. continuous-time filtering of the analog differential output is necessary using an off-chip amplifier and a few external passive components. at least 79db signal to noise plus distortion ratio can obtained in the frequency band of 0.425 x 9.6khz (with an oversampling ratio equal to 160). 2.2 receive a/d section the different functions included in the adc channel section are described below. 16-bit 2?s complement data format is used in the adc. 2.2.1 a/d converter the oversampled a/d converter is based on a second order sigma-delta modulator. to produce excellent common-mode rejection of unwanted signals, the analog signal is processed differentially until it is converted to digital data. single-ended mode can also be used. the adc is oversampled at 64, 96, 128, 160 or 192 x fs. the oversampling ratio is user selectable. at least -85db sndr can be expected in the 0.425 x 9.6khz bandwidth with a -6dbr differential input signal and an oversampling ratio equal to 160. 2.2.2 receive low pass filter it is a decimation filter. the decimation is performed by two decimation digital filters : one decimation fir filter and one decimation iir filter. the purpose of the fir filter is to decimate 32 times the digital signal coming from the adc modulator. fc 3db ? oclk 2 10 ?? --------------------- - = obsolete product(s) - obsolete product(s)
stlc7550 functional description rev 9 9/24 the iir is a cascade of 5 biquads. it provides the low-pass filtering needed to remove the noise remaining above half t he sampling frequency. the outpu t of the iir will be processed by the dsp. 2.3 clock generator the master clock, mclk is provided by the user thanks to a crystal or external clock generator (see figure 3 ). the mclk could be equal to 36.864mhz (mcm = 1). in that case thanks to the divider m x q, the stlc7550 is able to generate all v.34bis and 56 kbps sampling frequencies (see ta bl e 2 ). when mcm = 0, the mclk must be equal to the oversampling frequency : fs x over (7546 mode). the adc and dac are oversampled at the oclk frequency. oclk is equal to the shift clock used in the serial interface. the mclk frequency should be : mclk = k x sampling frequency combination of m, q and oversampling rati os allows to generate several sampling frequencies. recommended values for classical modem applications are as follow : note: 1 recommended value. table 2. sampling frequencies generation f (khz) fq = 36.864mhz (1) fq = 18.432mhz fq = 9.216mhz m q over m q over m q over 16.00 3 6 128 2 4.5 128 1 6 96 13.96 3 5.5 160 ------ 13.71 3 7 128 1 7 192 1 7 96 12.80 3 6 160 2 4.5 160 1 4.5 160 12.00 3 8 128 2 6 128 1 6 128 11.82 3 6.5 160 ------ 10.97 3 7 160 ------ 10.47 4 5.5 160 2 5.5 160 1 5.5 160 10.29 4 7 128 2 7 128 1 7 128 9.60 4 6 160 2 6 160 1 6 160 9.00 4 8 128 2 8 128 1 8 128 8.86 4 6.5 160 2 6.5 160 1 6.5 160 8.23 4 7 160 2 7 160 1 7 160 8.00 4 6 192 2 6 192 1 6 192 7.20 4 8 160 2 8 160 1 8 160 obsolete product(s) - obsolete product(s)
functional description stlc7550 10/24 rev 9 figure 3. clock block diagram 2.4 modes of operation thanks to mcm and m/s programmation pins we can get the following configuration. configuration 1 : mcm = 1, m/s = 1 the stlc7550 is in master mode and we have : fs = xtal in / (m x q x over) fs and sclk are output pins. figure 4. configuration 1 configuration 2 : mcm = 1, m/s = 0 the stlc7550 is in slave mode. sclk is provided by the stlc7550, the processor generates the fs and controls the phase of the sampling frequency. fs must be the result of a division of a nu mber of cycles of slck (fs = sclk % over). configuration 3 : mcm = 0, m/s = 1 the stlc7550 is in master mode and the processor provides the xtal in = mclk = oclk. the stlc7550 generates the fs from oclk. in this mode the configuration 3 is equivalent to the stlc7546 mode. configuration 4 : mcm = 0, m/s = 0 the stlc7550 is in slave mode. the configuration 4 is equivalent to configuration 3 but the fs is generated and phase controlled by the processor. bit 3-4-5 internal sampling m/s sync fs sclk (oclk) % over xtalin (mclk) xtalout m q mcm cont. reg. : bit 8-9-10-11-12-13 v dd sclk fs din dout bclk fs do di xtalin m/s mcm stlc7550 processor v dd f q = 36.864mhz v dd ts gnd obsolete product(s) - obsolete product(s)
stlc7550 functional description rev 9 11/24 figure 5. configuration 2 figure 6. configuration 3 (7546 mode) configuration 5 : mcm = 1, m/s = 1 (master codec) mcm = 0, m/s = 0 (slave codec) this is dual codec application. the master codec has his data in timeslot 0 and the slave codec has his data in timeslot 1 thanks to the programmation of ts. figure 7. configuration 4 sclk fs din dout bclk fs do di xtalin m/s mcm stlc7550 processor gnd v dd f q = 36.864mhz ts gnd sclk fs din dout xtalin m/s mcm stlc7550 v dd gnd f q = k x fs bclk fs do di processor ts gnd sclk fs din dout xtalin m/s mcm stlc7550 gnd f q = k x fs bclk fs do di processor gnd ts gnd obsolete product(s) - obsolete product(s)
functional description stlc7550 12/24 rev 9 figure 8. configuration 5 2.5 host interface the host interface consist of the shift cl ock, the frame synchronization signal, the adcchannel data output, and the dac-channel data input. two modes of serial transfer are available : ? first : software mode for 15-bit transmit data transfer and 16-bit receive data transfer ? second : hardware mode for 16-bit data transfer. both modes are selected by the hardware control pins (hc0, hc1). the data to the device, input/output are msb-first in 2?s complement format (see ta bl e 3 ). when control mode is selected , the device will internally ge nerate an addi tional frame synchronization pulse (secondary frame synchr onization pulse) at the midpoint of the original frame period. if the device is in slave mode the additional frame sync (secondary frame sync pulse) must be generated by the processor. the original frame synchronization pulse will also be referred to as th e primary frame synchronization pulse. sclk fs din dout bclk fs do di xtalin m/s mcm stlc7550 processor v dd f q = 36.864mhz ts fs din dout hc0 m/s mcm stlc7550 gnd hc0 xtakin v dd gnd v dd ts gnd hc1 hc1 table 3. mode selection hc1 hc0 lsb useful data secondary fsync description 0 0 0 15bits no software mode for data transfer only. 0 0 1 15bits (+16bits reg.) yes software mode for data transfer + control register transfer. obsolete product(s) - obsolete product(s)
stlc7550 functional description rev 9 13/24 figure 9. data mode figure 10. mixed mode 2.6 control register this section defines the control and device status information. the register programming occurs only during secondary frame synchronization. after a reset condition, the device is always in data mode. 0 1 x 16bits no hardware mode for data transfer only. 1 x x 16bits (+16bits reg.) yes hardware mode for data transfer + control register transfer. table 3. mode selection (continued) hc1 hc0 lsb useful data secondary fsync description d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 - d15 d14 - - - - fs sclk txdi hc1, hc0 sampling period 00 or 01 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 - d15 d14 - - - - txdo sampling period 1/2 sampling period (see note) fs txdi hc1, hc0 1x data word input control word 01 sclk txdo data word output register word note : in slave mode, this 1/2 sampling period is not mandatory. if 1/2 sampling period is not provided, one sample is lost. table 4. bits assignment bits name function reset value 0 - - 0 1 d1 aux/main input 0 2 d2 receive gain 0 obsolete product(s) - obsolete product(s)
functional description stlc7550 14/24 rev 9 note: 1 not recommended case. performances could be reduced. 3 d3 oversampling bit 0 0 4 d4 oversampling bit 1 0 5 d5 oversampling bit 2 0 6 d6 attenuator transmit bit 0 0 7 d7 attenuator transmit bit1 0 8 m m divider 1 9 q0 q0 divider 1 10 q1 q1 divider 0 11 q2 q2 divider 0 12 t0 m divider and test mode bit 0 0 13 t1 m divider and test mode bit 1 0 14 test2 test mode bit 2 0 15 test3 test mode bit 3 0 table 5. aux/main input d1 function 0 main receive input 1 auxiliary receive input table 6. receive gain d2 function differential input 0 0db gain (commun mode fixed) 1 +6db gain (commun mode non-fixed) single ended (one in put used, other at v cm ) 0 -6db gain (see note 1) 1 0db gain table 4. bits assignment (continued) bits name function reset value table 7. oversampling ratio d5 d4 d3 function 0 0 0 160 0 0 1 192 0 1 0 reserved 0 1 1 reserved obsolete product(s) - obsolete product(s)
stlc7550 functional description rev 9 15/24 this two bits must be set to 0 for normal operation. 1 0 0 reserved 1 0 1 64 1 1 0 96 1 1 1 128 table 8. transmit attenuation d7 d6 function 0 0 infinite 0 1 reserved 1 0 -6db 1 1 0db table 9. q divider clock generator d11 d10 d9 function 0 0 0 q divider = 5 0 0 1 q divider = 6 0 1 0 q divider = 7 0 1 1 q divider = 8 1 0 0 q divider = 4.5 1 0 1 q divider = 5.5 1 1 0 q divider = 6.5 1 1 1 q divider = 7.5 table 10. m divider clock generator d13 d12 d8 function 0 0 0 m divider = 3 0 0 1 m divider = 4 0 1 x reserved 1 0 x reserved 1 1 0 m divider = 1 1 1 1 m divider = 2 table 11. reserved mode d15 d14 function x x reserved for test table 7. oversampling ratio (continued) d5 d4 d3 function obsolete product(s) - obsolete product(s)
electrical specifications stlc7550 16/24 rev 9 3 electrical specifications unless otherwise noted, electrical characteri stics are specified over the operating range. typical values are given for v dd = 3v, t amb = 25c and for nominal master clock frequency mclk = 1.536mhz and oversampling ratio = 160. 3.1 absolute maximum ratings 3.2 nominal dc characteristics table 12. absolute maximum ratings (referenced to gnd) symbol parameter value unit v dd dc supply voltage -0.3, 7.0 v v i ,v in digital or analog input voltage -0.3, v dd +0.3 v i i ,i in digital or analog input current 1 ma i o digital output current 20 ma i out analog output current 10 ma t oper operating temperature 0, 70 c t stg storage temperature -40, 125 c p dmax maximum power dissipation 200 mw esd electrostatic discharge 2000 v table 13. nominal dc characteristics (v dd = 3v 5%, gnd = 0v, t a = 0 to 70c unless otherwise specified) symbol parameter min. typ. max. unit v dd supply voltage range 2.70 3 5.5 v power supply and common mode voltage single power supply (dv dd = av dd ) i dda analog supply current 6 ma i ddd digital supply current 4 ma i dd -lp supply current in low power mode mclk stopped mclk running 1 200 10 a v cm output common mode voltage v cm output voltage load current (see note 1) v dd /2-5% v dd /2 v dd /2+5% v digital interface v il low level input voltage -0.3 0.5 v v ih high level input voltage dv dd -0.5 v obsolete product(s) - obsolete product(s)
stlc7550 electrical specifications rev 9 17/24 note: 1 device is very sensitive to noise on v cm pin. v cm output voltage load current must be dc (<10a). in order to drive dynamic load, v cm must be buffered. ac variation in vcm current magnitude decrease a/d and d/a performance. 3.3 nominal ac electrical characteristics i i input current v i = v dd or v i = gnd -10 1 10 a v oh high level output voltage (i load = -600a) dv dd -0.5 v v ol low level output voltage (i load = 800a) 0.3 v analog interface v ref differential reference voltage output v ref = (v refp - v refn ) 1.15 1.25 1.35 v t coeff (v ref )v ref temperature coefficient 200 ppm/c v cmo in input common mode offset voltage v cmo in = [(in+)+(in-)]/2 -v cm -100 100 mv v dif in differential input voltage : [(in+)-(in-)] 2 x v ref 2 x v ref vpp v off in differential input dc offset voltage -100 100 mv v cmo out output common mode voltage offset : (out+ + out-)/2 - v cm (see note 1) -20 20 mv v dif out differential output voltage : out+ - out- 2 x v ref 2 x v ref v v off out differential output dc offset voltage : (out+ -out-) (0000x) -100 100 mv r in input resistance in+, in- (id. aux in) 100 k ? r out output resistance (out+, out-) 50 w r l load resistance (out+, out-) 10 k ? c l load capacitance (out+, out-) 20 pf v ado out output a/d modulator voltage offset: in+ = in- = v cm -1000 +1000 lsb table 13. nominal dc characteristics (continued) (v dd = 3v 5%, gnd = 0v, t a = 0 to 70c unless otherwise specified) symbol parameter min. typ. max. unit table 14. nominal ac electrical characteristics (reference level v il = 0.5v, v ih = dv dd - 0.5v, v ol = 0.3v, v oh = dv dd - 0.5v, dv dd = 3v, output load = 50pf unless otherwise) symbol n parameter mi n. typ. max. unit serial channel timing (see figure 11 for parameter numbers) 1 sclk period 300 ns 2 sclk width low 150 ns obsolete product(s) - obsolete product(s)
electrical specifications stlc7550 18/24 rev 9 figure 11. serial inte rface timing diagram 3 sclk width high 150 ns 4 sclk rise time 10 ns 5 sclk fall time 10 ns 6 fs setup 100 ns 7 fs hold 100 ns 8 din setup 50 ns 9 din hold 0 ns 10 dout valid 20 ns 11 hc0,hc1 set-up 20 ns 12 0 50 ns master clock interface (mclk) (mcm = 0) mclk master clock input 0.92 1.54 2.8 mhz master clock duty cycle 45 55 % table 14. nominal ac electrical characteristics (continued) (reference level v il = 0.5v, v ih = dv dd - 0.5v, v ol = 0.3v, v oh = dv dd - 0.5v, dv dd = 3v, output load = 50pf unless otherwise) symbol n parameter mi n. typ. max. unit sclk fs din 1 67 10 89 2.4 35 msb msb dout hc0 11 12 obsolete product(s) - obsolete product(s)
stlc7550 electrical specifications rev 9 19/24 3.4 transmit characteristics 3.4.1 performance of the tx channel note: 1 the dynamic range can be measured in bit with : nbit = with dr in db. 3.4.2 smoothing filter transfer characteristics the cut-off frequency of the single pole switch-capacitor low-pass filter following the dac is : with n = 2, 3, 4, 5, 6 (see section 2.1.1 ). 3.5 receive characteristics 3.5.1 performance of the rx channel table 15. performance of the tx channel typical values are given for av dd = 3v, t amb = 25c and for nominal master clock mclk = 1.536mhz, differential mode and oversampling ratio = 160. measurement band = 100hz to 0.425 x sampling frequency. symbol parameter min. typ. max. unit gabs absolute gain at 1khz -0.5 0 0.5 db ripple ripple in band : 0 to 0.425 x fs 0.2 db thd total harmonic distortion (differential tx signal : v out = 1.25v pp , f = 1khz) -85 -92 db dr dynamic range (f = 1khz) (measured over the full 0 to fs/2 with a -20dbr output signal and extrapolated to full scale) (see note 1) 87 db crxtx crosstalk (transmit channel to receive channel) 85 db dr 1.76 ? 6.02 -------------------------- fc 3db ? n32fs ?? 2 10 ?? -------------------------- - = table 16. performance of the rx channel typical values are given for av dd = 3v, t amb = 25c and for nominal master clock mclk = 1.536mhz, differential mode and oversampling ratio = 160. measurement band = 100hz to 0.425 x sampling frequency. symbol parameter min. typ. max. unit gabs absolute gain at 1khz -0.5 0 0.5 db ripple ripple in band : 0 to 0.425 x fs 0.2 db thd total harmonic distortion (differential tx signal : v out = 1.25vp p , f = 1khz) -85 -92 db dr dynamic range (f = 1khz) (measured over the full 0 to fs/2 with a -20dbr output signal and extrapolated to full scale) (see note 2) 87 db crxtx crosstalk (transmit channel to receive channel) 85 db obsolete product(s) - obsolete product(s)
typical application stlc7550 20/24 rev 9 4 typical application figure 12. line interface - differential duplexor all capacitor, resistor and impedance values are provided for indication only. these values must be readjusted according to line transformer characteristics and also telecommunication regulations in force in individual countries. refer to application note an 930 for more detailed information. contact your local representative. 22k ? 22k ? 100pf vcm 22k ? 22k ? 100pf 680pf 13.2k ? 13.2k ? out- out+ c' 1.2k ? 1.2k ? 2.2nf vcm 2.2nf c 2r z0/2 c 2r z0/2 r r phone line c : improve the low frequency response. its value depends on the transformer inductance. c' : reduces the dc offset gain. z0 : nominal line impedance in+ in- r' r r' obsolete product(s) - obsolete product(s)
stlc7550 definition and terminology rev 9 21/24 5 definition and terminology data transfer interval the time during which data is transfered from d out and to d in . this interval is 16 shift clocks provides by the chip. signal data this refers to the input signal and all the converted representations through the adc channel and the dac channel. data mode this refers to the data transfer. since the device is synchronous, the signal data words from the adc channel and to the dac channel occur simultaneously. control mode this refers to the digital control data transfer into din and the register read data from d out . the control mode interval occurs when requested by hardware or software. frame sync. frame sync refers only to the falling edge of the signal which initiates the data transfer interval. the primary frame sync starts the data mode and the secondary frame sync starts the control mode. frame sync and sampling period the time between falling edges of successive primary frame sync signals. adc channel this term refers to all signal processing circuits between the analog input and the digital conversion result at d out . dac channel this term refers to all signal processing circuits between the digital data word applied to d in and the differential output analog signal available at out+ and out-pins. oversampling ratio this term refer to the ratio between the master clock mclk corresponding to the oversampling frequency and the sampling frequency fs. resolution the number of bits in the input words to the dac, and the output words in the adc. dynamic range the s/(n+d) with a 1khz, -20dbr input signal and extrapolated to full scale. use of a small input signal reduces the harmonic distortion components of the noise to insignificance. units in db or in n bit as explained before. signal-to- (noise+distortion) s/(thd+n) is the ratio of the rms of the input signal to the rms of all other spectral components within the measurement bandwidth (0.425 x sampling frequency). units in db. crosstalk the amount of 1khz signal present on the output of the grounded input channel with 1khz 0db signal present on the other channel. units in db. power supply rejection ratio psrr. the amount of 1khz signal present on the output of the grounded input channel with 1khz 200mv pp signal present on the power supply. obsolete product(s) - obsolete product(s)
package information stlc7550 22/24 rev 9 6 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 13. tqfp48 (7 x 7 x 1.4mm) mechanical data & package dimensions body: 7 x 7 x 1.40mm dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.006 0.008 0.010 c 0.09 0.20 0.004 0.008 d 9.00 0.354 d1 7.00 0.276 d3 5.50 0.217 e 0.50 0.020 e 9.00 0.354 e1 7.00 0.276 e3 5.50 0.217 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (min.), 3.5?(typ.), 7 (max.) tqfp48 outline and mechanical data obsolete product(s) - obsolete product(s)
stlc7550 revision history rev 9 23/24 7 revision history table 17. document revision history date revision changes 14-jan-2004 8 initial release. 06-feb-2006 9 removed the tqfp44 package and the respective ordering part number. inserted the new part number E-STLC7550TQF7 (ecopack). obsolete product(s) - obsolete product(s)
stlc7550 24/24 rev 9 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com obsolete product(s) - obsolete product(s)

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